PIN SOI Diode Study by TCAD Simulation

PIN SOI Diode Study by TCAD Simulation

A.Graziele Harada Donatoa         C.Renato Giacominia         D.Rudolf Bühler a

a Centro Universitário FEI

e-mail: [e-mail]

1. Abstract

PIN Diodes have many applications, since optical communication, security systems, detection and gas classification, medical equipments and space observation. This project studied the voltage, light and temperature influence on a Lateral PIN SOI (Silicon-On-Insulator) Diode.

2. Introduction

The SOI technology refers to the use of a thin Silicon layer under device, separated from the substrate by a buried oxide to reduce parasitic effects caused by radiation [1]. The PIN SOI Diode (Fig. 1) is composed of anode (P+), intrinsic (P-) and cathode (N+) region.

[pic 1]

Fig. 1 Lateral PIN SOI Diode representation.

The size of depletion-region (RDD) can vary until the maximum size according to the biasing applied between P and N regions. When the diode is directly biased, the diffusion current overcome the drift current, then the RDD region decrease. During the reverse biasing, the drift current overcome the diffusal current, then the RDD region increase. With the diode biased reversely, when the RDD region is lighted, electron-hole pairs generated are separated by the electric field, and collected by anode and cathode before the recombination, increasing the photocurrent. And when substrate is biased, it is possible to change the operation mode of the intrinsic region among accumulation, depletion and inversion [2].

For different the temperatures, the dark current is affected as well as the diode’s performance.  The rise of temperatures increase the dark current by several orders of magnitude, as a result of increased thermal generation of electron-hole pairs [2].

3. Studied Device

Two-dimensional numerical simulations of the Lateral PIN SOI Diode were performed using the devices numerical simulator Sentaurus by Synopsys [3]. The device has the regions P and I with length 4,5µm and 8µm, respectively, and doping concentration NA 1020cm-3 end 1015cm-3, respectively. The region N has length 4,5µm and doping concentration ND 4x1020cm-3. The Silicon layer has thickness 80nm and the buried oxide’s thickness is 390nm [4].

4. Results

        The Figure 2 represents the cathode current (Icathode) in function of substrate voltage, with six anode biasing (Vanode), curves. The Figure enables to notice differents operation modes. Accumulation appears on substrate voltages under, approximately, -5V. Inversion over, approximately, 0V and depletion between -5V and 0V. To different anode voltages, there are different substrate voltages to maximum depletion.

[pic 2]

Fig. 2 Cathode current in function of substrate voltage.

        

        Comparing the Figures (2.a. and 2.b.), it is possible to see the light influence on cathode current. Light encreases the cathode current and, to low wave-lengths the cathode current is higher than to high wave-lenghts.