Projeto: Maquina de Bilhetes
Por: antoniojose13 • 31/3/2019 • Artigo • 5.189 Palavras (21 Páginas) • 245 Visualizações
Centro Universitário da FEI
Sistemas Digitais 3 Projeto 2: Maquina de Bilhetes
Nome: Victor Hugo Ferreira R.A 15.113.168-7
Rodrigo Yudji Katagiri de Oliveira R.A 11.114.054-7
São Bernardo do Campo
- Introdução
O projeto de sistemas digitais 3 está sendo uma máquina de bilhetes automatizada, que temos bilhetes de ida , ida e volta e um 1 dia, que foi desenvolvido via rede de petri e as especificações foram divididas para cada grupo com isso temos a construção da ideia do projeto a baixo iremos colocar a rede petri em blocos e o código VHDL .
- Rede de Petri
[pic 1]
- Código
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
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entity maquina_bilhete is
GENERIC (ck_divide: INTEGER := 200000); --200000 100MHz to 500Hz LCD
Port (clock : in STD_LOGIC;
reset : in STD_LOGIC;
CI : in STD_LOGIC;
CIV : in STD_LOGIC;
CDIA : in STD_LOGIC;
IDA : in STD_LOGIC; -- SW0
IV : in STD_LOGIC; -- SW1
DIA : in STD_LOGIC; -- SW2
M50c : in STD_LOGIC;
M1R : in STD_LOGIC;
RBILH : in STD_LOGIC;
RTROCO : in STD_LOGIC;
Ctroco : in STD_LOGIC;
IMOEDA : out STD_LOGIC;
SEM_IDA : out STD_LOGIC;
SEM_IV : out STD_LOGIC;
SEM_DIA : out STD_LOGIC;
SEM_TROCO : out STD_LOGIC;
TROCO_PRONTO : out STD_LOGIC;
BILHETE_PRONTO : out STD_LOGIC;
DB :out STD_LOGIC_VECTOR (7 downto 0); -- lcd
RS, RW : out STD_LOGIC; -- lcd
E : Buffer STD_LOGIC); -- lcd
end maquina_bilhete;
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architecture Behavioral of maquina_bilhete is
--- Binarias ---
signal P22SIN :std_logic;
signal FIXED :std_logic; --LUGAR SEMPRE COM UMA MARCA
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----------------SELEÇÃO DE BILHETE--------------------
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-- BILHETES
signal T6 :std_logic;
signal T7 :std_logic;
signal T8 :std_logic;
--VER SE POSSUI IDA
signal T0 :integer range 0 to 255;
signal LD7 :std_logic;
signal P0 :integer range 0 to 255;
--VER SE POSSUI IDA E VOLTA
signal T2 :integer range 0 to 255;
signal LD6 :std_logic;
signal P1 :integer range 0 to 255;
--VER SE POSSUI O 1DIA
signal T4 :integer range 0 to 255;
signal LD5 :std_logic;
signal P2 :integer range 0 to 255;
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----------------ETAPA DE PAGAMENTO-------------------
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signal P13 :integer range 0 to 255;
signal T20 :integer range 0 to 255;
signal LD0 :std_logic;
signal M10 :std_logic;
signal T10 :std_logic;
signal T9 :std_logic;
signal P17 :std_logic;
signal T17 :std_logic;
signal VT20 :integer range 0 to 255;
signal T25 :std_logic;
signal T18 :std_logic;
signal T6I :std_logic;
signal T7I :std_logic;
signal T8I :std_logic;
signal NP :std_logic;
signal P :std_logic;
SIGNAL SB :std_logic;
signal bcd_custo : std_logic_vector(9 downto 0); -- custo em codigo bcd
signal bcd_troco : std_logic_vector(9 downto 0); -- troco em codigo bcd
signal converte_custo : std_logic_vector(7 downto 0);
signal converte_troco : std_logic_vector(7 downto 0);
signal dezena, unidade, deztroco, unitroco : std_logic_vector(7 downto 0);
----- clock enable
signal cke : std_logic;
signal contador : integer range 0 to 50000000;
----- FSM lCD
TYPE state is (FunctionSet, ClearDisplay, DisplayControl, EntryMode, SetAddress,
WriteData1, WriteData2, WriteData3, WriteData4, WriteData5,
WriteData6, WriteData7, WriteData8, WriteData9, WriteData10,
WriteData17, WriteData18, WriteData19, WriteData20, WriteData21,
WriteData22, WriteData23, WriteData24, WriteData25, WriteData26,
WriteData27, WriteData28, ReturnHome);
signal pr_estado, estado: state;
type lcd_data is array (0 to 31) of std_logic_vector(7 downto 0);
...